module register_file(ra, rb, rw, busW, clear, write_enable, clk, busA, busB);

input [4:0] ra, rb, rw;
input [31:0] busW;
input clear, write_enable, clk;

output [31:0] busA, busB; 

reg [31:0] registers[31:0];

reg [31:0] i; 

assign busA = registers[ra];
assign busB = registers[rb];
	
initial begin
	for(i=0; i<32; i=i+1) begin
				registers[i] = 0;	
	end
end 	
		
always @ (negedge clk) begin

	if(clear) begin
			for(i=0; i<32; i=i+1) begin
				registers[i] = 32'b0;	
			end
	end

	if(write_enable) begin
		registers[rw] = busW;
	end
	$display (" register[%d]=%d | register[%d]=%d | register[%d]=%d\n", ra, registers[ra] , rb, registers[rb], rw, registers[rw]);
end
endmodule

/*
module m555(clock);
    parameter InitDelay = 5, Ton = 50, Toff = 50;
    output clock;
    reg clock;

    initial begin
        #InitDelay clock = 1;
    end

    always begin
        #Ton clock = ~clock;
        #Toff clock = ~clock;
    end
endmodule



module test_registerfile(ra, rb, rw, busW, clear, write_enable, clk, busA, busB);
	input clk;
	input [31:0] busA, busB; 
	output [4:0] ra, rb, rw;
	output [31:0] busW;
	output clear, write_enable;
	reg [4:0] ra, rb, rw;
	reg [31:0] busW;
	reg clear, write_enable;
	
	//output [31:0] busA, busB; 
	//reg [31:0] busA, busB; 
	
    initial begin
        $monitor ($time, " ra= %d, rb= %d, rw= %d, busW= %d, clear= %d, write_enable= %d, clk= %d, busA= %d, busB= %d", ra, rb, rw, busW, clear, write_enable, clk, busA, busB);
        clear=1; write_enable=1;
        #100 rw = 3; busW=25; clear=1; write_enable=1;
        #100 ra=3; rw=4; busW=12;
        #100 ra=4; rb=3; rw=5; busW=13;
        #100 ra=5; rb=16; rw=4; busW=14;
        #100 $finish;
    end
endmodule

module testBenchD;
    wire clock;
	wire [4:0] ra, rb, rw;
	wire [31:0] busW;
	wire clear, write_enable;
	wire [31:0] busA, busB; 
	
    m555 clk(clock);
    register_file dl(ra, rb, rw, busW, clear, write_enable, clock, busA, busB);
    test_registerfile td(ra, rb, rw, busW, clear, write_enable, clock, busA, busB);
	
endmodule
*/